Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?

Today we observe amazing performance achieved by Machine Learning (ML); for specific tasks it even surpasses human capabilities. Unfortunately, nothing comes for free: the hidden cost behind ML performance stems from its high complexity in terms of operations to be computed and the involved amount of data. For this reasons, custom Artificial Intelligence hardware accelerators based on alternative computing paradigms are attracting large interest. Such dedicated devices support the energy-hungry data movement, speed of computation, and memory resources that MLs require to realize their full potential. However, when ML is deployed on safety-/mission-critical applications, dependability becomes a concern. This paper presents the state of the art of custom Artificial Intelligence hardware architectures for ML, here Spiking and Convolutional Neural Networks, and shows the best practices to evaluate their dependability

Reliability Analysis of MTJ-based Functional Module for Neuromorphic Computing

International audienc

Challenges and Solutions in Emerging Memory Testing

International audienceThe research and prototyping of new memory technologies are getting a lot of attention in order to enable new (computer) architectures and provide new opportunities for today’s and future applications. Delivering high quality and reliability products was and will remain a crucial step in the introduction of new technologies. Therefore, appropriate fault modelling, test development and design for testability (DfT) is needed. This paper overviews and discusses the challenges and the emerging solutions in testing three classes of memories: 3D stacked memories, Resistive memories and Spin-Transfer-Torque Magnetic memories. Defects mechanisms, fault models, and emerging test solutions will be discussed

Stuck-At Fault Mitigation of Emerging Technologies Based Switching Lattices

Switching lattices are two-dimensional arrays composed of two or four-terminals switches organized as a crossbar array. The idea of using regular two-dimensional arrays of switches for Boolean function implementation was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Emerging technologies allow more complex function integration, thanks to their smaller sizes and advanta geous properties such as zero leakage current, capability to retain data when in power-off state, and almost unlimit edendurance, to name just a few appealing features. Also, implementation of new computing paradigms combining memory and logic becomes possible. However, emerging technologies show a non-negligible defect ratio and higher sensitivity to process and environment variations. The reliability challenges in adopting these technologies need to be investigated. In this paper, we analyze the resilience of switching lattices to stuck-at-fault model (SAF). We first identify the critical switches through an elaborated sensitivity methodology and extensive analysis of the lattice. Next, we propose several techniques to improve lattice resilience in the face of these types of faults, that can be implemented after lattice logic optimization steps

Fault Mitigation of Switching Lattices under the Stuck-At-Fault Model

Switching lattices are two-dimensional arrays composed by four-terminal switches (crossbar arrays). The idea of using regular two-dimensional arrays of switches to implement Boolean functions was proposed by Akers in 1972. Recently, with the advent of a variety of emerging nanoscale technologies, lattices have found a renewed interest. Switching lattices can have a non-negligible defective ratio. In this paper, we analyze the fault tolerance of switching lattices under the stuck-at-fault model (SAFM). We first identify the critical switches with a sensitivity analysis of the lattice. We then propose some techniques to improve the resilience to faults, which are implemented as a post preprocessing step after logic optimization

Ethnicity and wage determination in Ghana

SIGLEAvailable from British Library Document Supply Centre-DSC:9350.8339(WPS/2000-9) / BLDSC - British Library Document Supply CentreGBUnited Kingdo

STT-MRAM-based PUF architecture exploiting magnetic tunnel junction fabrication-induced variability

Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement lowcost device authentication and secure secret key generation. Weak PUFs (i.e., devices able to generate a single signature or to deal with a limited number of challenges) are widely discussed in literature. One of the most investigated solutions today is based on SRAMs. However, the rapid development of low-power, high-density, high-performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. In this article, we propose an innovative PUF design based on STT-MRAM memory. We exploit the high variability affecting the electrical resistance of the Magnetic Tunnel Junction (MTJ) device in anti-parallel magnetization. We will demonstrate that the proposed solution is robust, unclonable, and unpredictable